This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Some schemes for write assist have been suggested for lowering core voltage supply (Vddc). However, these conventional schemes may be difficult to implement. For example, some of these schemes rely on a voltage divider to generate an intermediate value of Vddc that is lower than a full core voltage supply. As such, this scheme suffers from huge DC power aggregation during generation of the intermediate voltage in each bitcell column, which results in huge dynamic power during a write operation.
In another example, some of these schemes offer a solution that uses charge sharing between fully charged Vddc and a pre-discharged capacitor with assist of a route over a core bitcell array. Even though this scheme may not utilize a DC path, area penalty of this scheme is significantly large. As such, there exists a need to improve conventional schemes for lowering Vddc write assist in memory applications.